1. Field of Invention
The present invention relates to a non-volatile memory and an operation method thereof More particularly, the present invention relates to a non-volatile memory having a multi-level cell that includes multiple storage positions and an operation method thereof.
2. Description of Related Art
A charge trapping memory (NBit) is a nitride structure memory using silicon nitride as a charge trapping layer instead of using a polysilicon floating gate, in which a single NBit memory cell may have two separate charge bits according to a localized charge trapping technique, so as to form a so-called 2 bits/cell storage scheme. Further, by respectively programming the two bits of the NBit memory cell to a plurality of levels, the NBit memory cell may also serve as a multi-level cell (MLC).
During the operation of an NBit memory cell, the two bits in a same memory cell influence each other leading to an erroneous reading. Alternatively speaking, if one side of the NBit memory cell is stored with a bit and the other side of the NBit memory cell is read, a current of an originally high current part can be decreased, which leads to a so-called second-bit effect. Namely, when a read operation is performed to the NBit memory cell, the originally existed bit can influence the memory cell to increase a read threshold voltage (Vt). In this case, the read error problem is likely to occur.
FIG. 1 is a diagram illustrating a threshold voltage distribution of a conventional nitride structure MLC. As shown in FIG. 1, curves 110-140 are threshold-voltage distribution curves when a state of the memory cell is respectively level 1 to level 4. If a first storage position of the NBit memory cell is maintained at level 1, a second storage position of the NBit memory cell is programmed to level 2, and the threshold voltage distribution curve of the first storage position maintained at level 1 is shifted due to the second-bit effect, and the degree of shifting is shown by curve 150. Similarly, curves 160 and 170 respectively represent the degree of shifting of the threshold voltage distribution curve of the first storage position maintained at level 1 that is generated due to the second-bit effect when the second storage position of the NBit memory cell is respectively programmed to level 3 and level 4.
As shown in FIG. 1, the higher level the second storage position is programmed to, the more severe the second-bit effect is. For example, when the second storage position is programmed to level 4, the threshold voltage shift curve 170 of the first storage position generated due to the second-bit effect partially overlaps with the threshold voltage distribution curve 120. If the NBit memory cell is read now, the level 1 first storage position can be misjudged to be level 2, the device reliability is decreased. Moreover, the second-bit effect further reduces a read sense margin of the memory and a threshold-voltage window for operating the right and left bits, so that operation of the MLC becomes more difficult.